[Solved] Verilog

[Pedz]

Bit a of a longshot, but if anyone here knows verilog, need a bit of help

Basically, trying to initiate a module (left_rotation) inside a loop and starting on each positive clock. e.g

Code: Select all

genvar i;

 always @(posedge clk) begin

    if (req = 1) begin
       
        for(i=0; i<17;i= i+1) begin
            left_rotate("all the inputs/outputs")
            "makeoutputs next inputs, by assigning"
        end      

    end

Keep getting malfunction errors...
Any help would be great , purposely didnt copy the code here because I don't just want the answer, kinda want to know how it works so I may replicate it later and use it properly.

So basically would like to know how to instantiate modules within always/if/for loops.

Also don't know if this is 'off-topic' or software related :S, so posted it here, feel free to move if required.

[LITOralis.nMd]

EDIT: fail.

[Pedz]

I found my problem finally! I have to just put the inputs <= outputs inside the always/if statement, and the module outside. (as well as some other stuff ). As this automatically calls the function...

[BloodyDeed]

Good to hear, going to lock the thread.
Thanks for posting how you fixed it.